Semiconductor device fabrication requires techniques which grow one or more epitaxial layers on a substrate which is frequently referred to as a wafer. Accordingly, various epitaxial growth techniques have been developed including techniques such as liquid phase epitaxy and molecular beam epitaxy. The latter technique, commonly referred to as MBE, is capable of growing, for example, very thin layers with precisely controlled dimensions and doping concentrations.
However, for many device fabrication sequences, further processing of the layers is required after the first epitaxial layers are grown. This processing may include patterning of the surface by depositing a layer of resist and selectively forming openings in the resist, i.e., a pattern is formed in the resist which exposes portions of the surface of the top epitaxial layer. The now exposed suface may now be further processed by, for example, ion implanting in the exposed portions. Alternatively, the exposed material may be selectively removed.
Some processing steps might be eliminated and greater flexibility obtained in the device processing if single crystal material could be grown on selected areas of the wafer. Accordingly, selective area growth techniques have been developed. One such technique is described in the Journal of Applied Physics, 46, pp. 783-785, 1975. In this technique, a layer of amorphous SiO.sub.2 is deposited on an epitaxial layer of a Group III-V compound semiconductor and patterned to expose selected portions of the epitaxial layer. During the subsequent growth by MBE, polycrystalline material is formed on the amorphous material while high quality singel crystal material grows in the exposed areas opened by the SiO.sub.2 mask. This is a desirable structure because the polycrystalline semiconductor material is highly resistive, and can be used for dielectric isolation. That is, the single crystal material can be further processed to form devices which are electrically isolated from each other by the polycrystalline material.
While the above-described selective area growth technique is advantageously employed for many device fabrication steps, it is not fully satisfactory for all devices because some necessary fabrication steps cannot proceed unless the polycrystalline material is removed. The problem of removing polycrystalline material from the wafer may be avoided by using patterned Si shadow masks. The unwanted polycrystalline material is deposited on the mask and not on the wafer. These mechanical masks are not, however, totally practical for integrated circuit fabrication. Micron size features are involved, and, although masks with 1 .mu.m features have been made, masks with complex patterns are difficult to fabricate. Additionally, successive processing steps require mask alignment with respect to the previous layer to within a fraction of a micron. Alignment is often made still more difficult because a silicon mask and a Group III-V compound semiconductor typically have different thermal expansion coefficients. These make precise alignment over large areas extremely difficult because it is difficult to maintain the wafer and mask at the same temperature.
One approach to solving the problem created by the presence of the polycrystalline material uses selective etches which remove the polycrystalline and single crystal material at different rates. Lift-off techniques are, however, preferable because they leave the selectively grown single crystal portions of the wafer unaffected, i.e., little or no single crystal material is removed. Such a lift-off technique has been demonstrated for GaAs MBE using SiO.sub.2 as the masking material. See, for example, U.S. Pat. No. 4,111,725 issued on Sept. 5, 1978 to Cho, DiLorenzo and Mahoney.
While this is an attractive technique, it is somewhat disadvantageous because the wafer is typically removed from the ultra high vacuum MBE growth chamber to deposit the SiO.sub.2. This means that the epitaxial layer may be contaminated after removal from the growth chamber and prior to deposition of the amorphous SiO.sub.2 layer.